View 420AR-32_1398034.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

functional block diagram ad420 v cc 4k w 40 w boost i out v out fault detect gnd cap 1,2,3 offset trim v ll ref out ref in data out clear latch clock data in range select 1 range select 2 1.25k w reference clock 16-bit dac data i/p register switched current sources and filtering rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a serial input 16-bit 4C20 ma, 0C20 ma dac features 4C20 ma, 0C20 ma or 0C24 ma current output 16-bit resolution and monotonicity 6 0.012% max integral nonlinearity 6 0.05% max offset (trimmable) 6 0.15% max total output error (trimmable) flexible serial digital interface (3.3 mbps) on-chip loop fault detection on-chip 5 v reference (25 ppm/ 8 c max) asynchronous clear function maximum power supply range of 32 v output loop compliance of 0 v to v cc C 2.5 v 24-pin soic and pdip packages product description the ad420 is a complete digital to current loop output con- verter, designed to meet the needs of the industrial control mar- ket. it provides a high precision, fully integrated, low cost single-chip solution for generating current loop signals in a com- pact 24-pin soic or pdip package. the output current range can be programmed to 4 maC20 ma, 0 maC20 ma or an overrange function of 0 maC24 ma. the ad420 can alternatively provide a voltage output from a sepa- rate pin that can be configured to provide 0 vC5 v, 0 vC10 v, 5 v or 10 v with the addition of a single external buffer amplifier. the 3.3m baud serial input logic design minimizes the cost of galvanic isolation and allows for simple connection to com- monly used microprocessors. it can be used in three-wire or asynchronous mode and a serial-out pin is provided to allow daisy chaining of multiple dacs on the current loop side of the isolation barrier. the ad420 uses sigma-delta ( sd ) dac technology to achieve 16-bit monotonicity at very low cost. full-scale settling to 0.1% occurs within 3 ms. the only external components that are required (in addition to normal transient protection circuitry) are three low cost capacitors which are used in the dac output filter. if the ad420 is going to be used at extreme temperatures and supply voltages, an external output transistor can be used to minimize power dissipation on the chip via the boost pin. the fault detect pin signals when an open circuit occurs in the loop. the on-chip voltage reference can be used to supply a precision +5 v to external components in addition to the ad420 or, if the user desires temperature stability exceeding 25 ppm/ c, an external precision reference such as the ad586 can be used as the reference. ? analog devices, inc., 1995 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 ad420 the ad420 is available in a 24-pin soic and pdip over the in- dustrial temperature range of C40 c to +85 c. product highlights 1. the ad420 is a single chip solution for generating 4 maC 20 ma or 0 maC20 ma signals at the controller end of the current loop. 2. the a d420 is specified with a power supply range from 12 v to 32 v. output loop compliance is 0 v to v cc C 2.5 v. 3. the flexible serial input can be used in three-wire mode with spi* or microwire? microcontrollers, or in asyn- chronous mode which minimizes the number of control signals required. 4. the serial data out pin can be used to daisy chain any num- ber of ad420s together in three-wire mode. 5. at power-up the ad420 initializes its output to the low end of the selected range. 6. the ad420 has an asynchronous clear pin which sends the output to the low end of the selected range (0 ma, 4 ma, or 0 v). 7. the ad420 boost pin accommodates an external transis- tor to off-load power dissipation from the chip. 8. the offset of 0.05% and total output error of 0.15% can be trimmed if desired, using two external potentiometers. *spi is a registered trademark of motorola. ?mlcrowire is a registered trademark of national semiconductor.
rev. c C2C (t a = t min Ct max , v cc = + 24 v, r l = 500 v , unless otherwise noted) ad420Cspecifications ax-32 versions 1 parameter min typ max units comments resolution 16 bits accuracy 2 monotonicity 16 bits integral nonlinearity 0.002 0.012 % offset (0 ma or 4 ma) (t a = +25 c) 0.05 % offset drift 20 50 ppm/ c total output error (20 ma or 24 ma) (t a = +25 c) 0.15 % total output error drift 20 50 ppm/ c psrr 3 510 m a/v output characteristics operating current ranges 4 20 ma 020ma 024ma current loop voltage compliance 0 v cc C 2.5 v v output voltage range (pin 17) 0 5 v settling time (to 0.1% of fs) 4 2.5 3 ms output impedance (current mode) 25 m w voltage reference ref out output voltage (t a = +25 c) 4.995 5.0 5.005 v drift 25 ppm/ c externally available current 5 ma short circuit current 7 ma ref in resistance 30 k w v ll output voltage 4.5 v externally available current 5 ma short circuit current 20 ma digital inputs v ih (logic 1) 2.4 v v il (logic 0) 0.8 v i ih (v in = 5.0 v) 10 m a i il (v in = 0 v) 10 m a data input rate (3-wire mode) no minimum 3.3 mbps data input rate (asynchronous mode) no minimum 150 kbps digital outputs fault defect v oh (10 k w pull-up resistor to v ll ) 3.6 4.5 v v ol (10 k w pull-up resistor to v ll ) 0.2 0.4 v v ol @ 2.5 ma 0.6 v data out v oh (i oh = C0.8 ma) 3.6 4.3 v v ol (i ol = 1.6 ma) 0.3 0.4 v power supply operating range v cc 12 32 v quiescent current 4.2 5.0 ma quiescent current (external v ll ) 3ma temperature range specified performance C40 +85 c notes 1 x refers to the package designator, r or n. 2 total output error includes offset and gain error. total output error and offset error are with respect to the full-scale output and are measured with an ideal +5 v reference. if the internal reference is used, the reference errors must be added to the offset and total output errors. 3 psrr is measured by varying v cc from 12 v to its maximum 32 v. 4 external capacitor selection must be as described in figure 5. specifications subject to change without notice.
rev. c C3C ad420 absolute maximum ratings* v cc to gnd ad420ar/an-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 v i out to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v cc digital inputs to gnd . . . . . . . . . . . . . . . . . . . C0.5 v to +7 v digital output to gnd . . . . . . . . . . . . . C0.5 v to v ll + 0.3 v v ll and ref out: outputs safe for indefinite short to ground. storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . +300 c thermal impedance: soic (r) package . . . . . . . . . . . . . . . . . . . . . . q ja = 75 c/w pdip (n) package . . . . . . . . . . . . . . . . . . . . . . q ja = 50 c/w * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide temperature max operating package model range voltage option* ad420an-32 C 40 c to +85 c 32 v n-24 ad420AR-32 C 40 c to +85 c 32 v r-24 *n = plastic dip, r = plastic soic. pin designations 13 16 15 14 24 23 22 21 20 19 18 17 top view (not to scale) 12 11 10 9 8 1 2 3 4 7 6 5 ad420 nc = no connect nc cap2 cap3 v cc nc v ll fault detect range select 2 i out boost cap1 range select 1 clear latch clock data in data out ref in offset trim v out gnd nc ref out nc warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad420 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ad420 v cc 4k w 40 w boost i out v out fault detect gnd cap 1,2,3 offset trim v ll ref out ref in data out clear latch clock data in range select 1 range select 2 1.25k w reference clock 16-bit dac data i/p register 19 20 21 22 23 14 15 16 17 18 6 7 8 9 10 11 2 3 4 5 switched current sources and filtering figure 1. functional block diagram table i. truth table inputs range range clear select 2 select 1 operation 0 x x normal operation 1 x x output at bottom of span x 0 0 0 vC5 v range x 0 1 4 maC20 ma range x 1 0 0 maC20 ma range x 1 1 0 maC24 ma range
rev. c C4C ad420 timing requirements (t a = C40 8 c to +85 8 c, v cc = +12 v to +32 v) three-wire interface clock data in word "n" word "n + 1" 1011001 111 00 00 11 00 11 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (lsb) (msb) b15 b14 b13 b12 latch data out clock 01 11 b15 b14 b13 b12 word "n" word "n ?1" data in latch data out t cl t ck t ch t ds t dh t dw t lh t ll t ld t sd figure 2. timing diagram for three-wire interface table ii. timing specification for three-wire interface parameter label limit units data clock period t ck 300 ns min data clock low time t cl 80 ns min data clock high time t ch 80 ns min data stable width t dw 125 ns min data setup time t ds 40 ns min data hold time t dh 5 ns min latch delay time t ld 80 ns min latch low time t ll 80 ns min latch high time t lh 80 ns min serial output delay time t sd 225 ns max clear pulse width t clr 50 ns min clock data in clock data in t adh t ack t adw t acl t ads start bit 01 1 0 0 bit 15 bit 14 bits 13-1 bit 0 stop bit next start bit (internally generated latch) expanded time view below clock counter starts here confirm start bit sample bit 15 0 1 2 8 16 24 start bit data bit 15 bit 14 expanded time view below t ach clock data in figure 3. timing diagram for asynchronous interface table iii. timing specifications for asynchronous interface parameter label limit units asynchronous clock period t ack 400 ns min asynchronous clock low time t acl 50 ns min asynchronous clock high time t ach 150 ns min data stable width (critical clock edge) t adw 300 ns min data setup time (critical clock edge) t ads 50 ns min data hold time (critical clock edge) t adh 20 ns min clear pulse width t clr 50 ns min msb (d15) is sampled 24 clock cycles after the beginning of the start bit, d14 is sampled at clock number 40, and so on. during any dead time before writing the next word the data in pin must remain at logic 1. the dac output updates when the stop bit is received. in the case of a framing error (the stop bit sampled as a 0) the ad420 will output a pulse at the data out pin one clock pe- riod wide during the clock period subsequent to sampling the stop bit. the dac output will not update if a framing error is detected. asynchronous interface note in the timing diagram for asynchronous mode operation each data word is framed by a start (0) bit and a stop (1) bit. the data timing is with respect to the rising edge of the clock at the center of each bit cell. bit cells are 16 clocks long, and the first cell (the start bit) begins at the first clock following the leading (falling) edge of the start bit. thus the
rev. c C5C ad420 pin description pin # symbol function 2v ll auxiliary buffered +4.5 v digital logic voltage. this pin is the internal supply voltage for the digital circuitry and can be used as a termination for pull-up resistors. an external +5 v power supply can be connected to v ll . it will override this buffered voltage, thus reducing the internal power dissipation. 3 fault detect fault detect, connected to a pull-up resistor, is asserted low when the output current does not match the dacs programmed value, for example, in case the current loop is broken. 4 range select 2 selects the converters output operating range. one output voltage range and three 5 range select 1 output current ranges are available. 6 clear valid v ih will unconditionally force the output to go to the minimum of its programmed range. after clear is removed the dac output will remain at this value. the data in the input register is unaffected. 7 latch in the three-wire interface mode a rising edge parallel loads the serial input register data into the dac. to use the asynchronous mode connect latch through a current limiting resistor to v cc . 8 clock data clock input. the clock period is equal to the input data bit rate in the three- wire interface mode and is 16 times the bit rate in asynchronous mode. 9 data in serial data input. 10 data out serial data output. in the three-wire interface mode, this output can be used for daisy-chaining multiple ad420s. in the asynchronous mode a positive pulse will indicate a framing error after the stop-bit is received. 11 gnd ground (common). 14 ref out +5 v reference output. 15 ref in reference input. 16 offset trim offset adjust. 17 v out voltage output. 18 i out current output. 19 boost connect to an external transistor to reduce the power dissipated in the ad420 output transistor, if desired. 20 cap 1 these pins are used for internal filtering. connect capacitors between each of these 21 cap 2 pins and v cc . refer to the description of current output operation. 22 cap 3 23 v cc power supply input. 1, 12, 13, 24 nc no connection. no internal connections inside device. definitions of specifications resolution: for 16-bit resolution, 1 lsb = 0.0015% of the fsr. in the 4 maC20 ma range 1 lsb = 244 na. integral nonlinearity: analog devices defines inte- gral nonlinearity as the maximum deviation of the actual, ad- justed dac output from the ideal analog output (a straight line drawn from 0 to fs C 1 lsb) for any bit combination. this is also referred to as relative accuracy. differential nonlinearity: differential nonlinearity is the measure of the change in the analog output, normalized to full scale, associated with an lsb change in the digital input code. monotonic behavior requires that the differential linearity error be greater than C1 lsb over the temperature range of interest. monotonicity: a dac is monotonic if the output either increases or remains constant for increasing digital inputs with the result that the output will always be a single-valued function of the input. gain error: gain error is a measure of the output error be- tween an ideal dac and the actual device output with all 1s loaded after offset error has been adjusted out. offset error: offset error is the deviation of the output current from its ideal value expressed as a percentage of the full- scale output with all 0s loaded in the dac. drift: drift is the change in a parameter (such as gain and offset) over a specified temperature range. the drift temperature coefficient, specified in ppm/ c, is calculated by measuring the parameter at t min , 25 c, and t max and dividing the change in the parameter by the corresponding temperature change. current loop voltage compliance: the voltage compliance is the maximum voltage at the i out pin for which the output current will be equal to the programmed value.
rev. c C6C ad420 theory of operation the ad420 uses a sigma-delta ( sd ) architecture to carry out the digital-to-analog conversion. this architecture is particularly well suited for the relatively low bandwidth requirements of the industrial control environment because of its inherent monoto- nicity at high resolution. in the ad420 a second order modulator is used to keep com- plexity and die size to a minimum. the single bit stream from the modulator controls a switched current source that is then filtered by three, continuous time resistor-capacitor sections. the capacitors are the only external components that have to be added for standard current-out operation. the filtered current is amplified and mirrored to the supply rail so that the application simply sees a 4 maC20 ma, 0 maC20 ma, or 0 maC24 ma current source output with respect to ground. the ad420 is manufactured on a bicmos process that is well suited to implementing low voltage digital logic with high performance and high voltage analog circuitry. the ad420 can also provide a voltage output instead of a cur- rent loop output if desired. the addition of a single external amplifier allows the user to obtain 0 vC5 v, 0 vC10 v, 5 v, or 10 v. the ad420 has a loop fault detection circuit that warns if the voltage at i out attempts to rise above the compliance range, due to an open-loop circuit or insufficient power supply voltage. the fault detect is an active low open drain signal so that one can connect several ad420s together to one pull-up resistor for global error detection. the pull-up resistor can be tied to the v ll pin, or an external +5 v logic supply. the i out current is controlled by a pmos transistor and inter- nal amplifier as shown in the functional block diagram. the in- ternal circuitry that develops the fault output avoids using a comparator with window limits since this would require an actual output error before the fault detect output be- comes active. instead, the signal is generated when the internal amplifier in the output stage of the ad420 has less than ap- proximately one volt remaining of drive capability (when the gate of the output pmos transistor nearly reaches ground). thus the fault detect output activates slightly before the compliance limit is reached. since the comparison is made within the feedback loop of the output amplifier, the output ac- curacy is maintained by its open-loop gain, and no output error occurs before the fault detect output becomes active. the three-wire digital interface, comprising data in, clock, and latch, interfaces to all commonly used serial microprocessors without the addition of any external glue logic. data is loaded into an input register under control of clock and is loaded to the dac when latch is strobed. if a user wants to minimize the number of galvanic isolators in an intrin- sically safe application, the ad420 can be configured to run in asynchronous mode. this mode is selected by connecting the latch pin to vcc through a current limiting resistor. the data must then be combined with a start and stop bit to frame the information and trigger the internal latch signal. ad420 v cc 4k w 40 w boost i out v out fault detect gnd cap 1,2,3 offset trim v ll ref out ref in data out clear latch clock data in range select 1 range select 2 1.25k w reference clock 16-bit dac data i/p register 19 20 21 22 23 14 15 16 17 18 6 7 8 9 10 11 2 3 4 5 switched current sources and filtering figure 4. functional block diagram
rev. c C7C ad420 applications current output the ad420 can provide 4 maC20 ma, 0 maC20 ma, or 0 maC 24 ma output without any active external components. the three capacitors shown in figure 5 are all that is required. these can be any type of low cost ceramic capacitors. to meet the specified full-scale settling time of 3 ms, low dielectric absorp- tion capacitors (npo) are required. suitable values are c1 = 0.01 m f, c2 = 0.01 m f, and c3 = 0.0033 m f. 5 2 4 6 7 8 9 c1 c2 c3 v cc 20 21 22 23 v ll i out (4-20ma) rload ref out ref in 15 14 11 gnd range select 1 range select 2 clear latch clock data in ad420 18 figure 5. standard configuration driving inductive loads when driving inductive or poorly defined loads connect a 0.01 m f capacitor between i out (pin 18) and gnd (pin 11). this will ensure stability of the ad420 with loads beyond 50 mh. there is no maximum capacitance limit. the capacitive component of the load may cause slower settling, though this may be masked by the settling time of the ad420. a pro- grammed change in the current may cause a back emf voltage on the output that may exceed the compliance of the ad420. to prevent this voltage from exceeding the supply rails connect protective diodes between i out and each of v cc and gnd. voltage-mode output since the ad420 is a single supply device, it is necessary to add an external buffer amplifier to the v out pin to obtain a selec- tion of high quality bipolar output voltage ranges as shown in figure 6. 6 7 8 9 c1 c2 c3 v cc 20 21 22 23 v out r2 ref out ref in 15 14 11 gnd range select 1 range select 2 clear latch clock data in ad420 17 4 5 r1 r3 v out figure 6. table iv. buffer amplifier configuration r1 r2 r3 v out open open 0 0 vC5 v open r r 0 vC10 v r open r 5 v r2r2r 10 v suitable r = 5 k w . optional span and zero trim for those users who would like lower than specified values of offset and gain error, figure 7 shows a simple way to trim these parameters. care should be taken to select low drift resistors be- cause they will affect the temperature drift performance of the dac. the adjustment algorithm is iterative. the procedure for trim- ming the ad420 in the 4C20 ma mode can be accomplished as follows: step i . . . offset adjust load all zeros. adjust rzero for 4.00000 ma of output current. step ii . . . gain adjust load all ones. adjust rspan for 19.99976 ma (fs C 1 lsb) of output current. return to step i and iterate until convergence is obtained. 6 7 8 9 c1 c2 c3 v cc 20 21 22 500 w rspan 15 11 gnd range select1 range select2 clear latch clock data in ad420 19 4 2 v ll i out (4-20ma) rload 18 5k w rspan2 v ref 14 23 16 10k w rzero 5 boost figure 7. offset and gain adjust
rev. c C8C ad420 three-wire interface figure 8 shows the ad420 connected in the three-wire interface mode. the ad420 data input block contains a serial input shift register and a parallel latch. the contents of the shift register are controlled by the data in signal and the rising edges of the clock. upon request of the latch pin the dac and inter- nal latch are updated from the shift register parallel outputs. the clock should remain inactive while the dac is updated. refer to the timing requirements for three-wire interface. rload fault detect v cc latch clock data in gnd data out i out ad420 dac1 v cc latch v ll v cc fault detect clock data in gnd data out ad420 dac2 i out 10k w fault detect v cc rload latch clock data in figure 8. three-wire interface using multiple dacs with joint fault detect using multiple dacs with fault detect the three-wire interface mode can utilize the serial data out for easy interface to multiple dacs. to program the two ad420s in figure 8, 32 data bits are required. the first 16 bits are clocked into the input shift register of dac1. the next 16 bits transmitted pass the first 16 bits from the data out pin of dac1 to the input register of dac2. the input shift regis- ters of the two dacs operate as a single 32-bit shift register, with the leading 16 bits representing information for dac2 and the trailing 16 bits serving for dac1. each dac is then up- dated upon request of the latch pin. the daisy-chain can be extended to as many dacs as required. asynchronous interface using optocouplers the ad420 connected in asynchronous interface mode with optocouplers is shown in figure 9. asynchronous operation minimizes the number of control signals required for isolation of the digital system from the control loop. the resistor connected between the latch pin and v cc is required to acti- vate this mode. for operation with v cc below 18 v use a 50 k w pull-up resistor, from 18 vC32 v use 100 k w . asynchronous mode requires that the clock run at 16 times the data bit rate, ther efore to operate at the maximum input data rate of 150 kbps an input clock of 2.4 mhz is required. the actual data rate achieved may be limited by the type of optocouplers chosen. the number of control signals can further be reduced by creat- ing the appropriate clock signal on the current loop side of the isolation barrier. v cc gnd latch clock data in v ll clock +5v data isolation galvanic barrier +24v 11 2 8 23 7 9 100k w figure 9. asynchronous interface using optocouplers
rev. c C9C ad420 microprocessor interface sec tion ad420 to mc68hc11 (spi bus) interface the ad420 interface to the motorola spi (serial peripheral in- terface) is shown in figure 10. the mosi, sck, and ss pins of the hc11 are respectively connected to the data in, clock, and latch pins of the ad420. the majority of the interfacing issues are done in the software initialization. a typi- cal routine such as the one shown below begins by initializing the state of the various spi data and control registers. init ldaa #$2f ; ss = 1; sck = 0; mosi = 1 staa portd ;send to spi outputs ldaa #$38 ; ss , sck,mosi = outputs staa ddrd ;send data direction info ldaa #$50 ;dabl intrpts,spi is master & on staa spcr ;cpol = 0, cpha = 0, 1mhz baudrate nextpt ldaa msby ;load accum w/upper 8 bits bsr sendat ;jump to dac output routine jmp nextpt ;infinite loop sendat ldy #$1000 ;point at on-chip registers bclr $08,y,$20 ;drive ss (latch) low staa spdr ;send ms-byte to spi data reg wait1 ldaa spsr ;check status of spie bpl wait1 ;poll for end of x-mission ldaa lsby ;get low 8 bits from memory staa spdr ;send ls-byte to spi data reg wait2 ldaa spsr ;check status of spie bpl wait2; ;poll for end of x-mission bset $08,y,$20 ;drive ss high to latch data rts the spi data port is configured to process data in 8-bit bytes. the most significant data byte (msby) is retrieved from memory and processed by the sendat routine. the ss pin is driven low by indexing into the portd data register and clear bit 5. the msby is then sent to the spi data register where it is automatically transferred to the ad420 internal shift resister. the hc11 generates the requisite eight clock pulses with data valid on the rising edges. after the msby is transmitted, the least significant byte (lsby) is loaded from memory and trans- mitted in a similar fashion. to complete the transfer, the latch pin is driven high when loading the complete 16-bit word into the ad420. data in clock latch mosi sck ss ad420 68hc11 figure 10. ad420 to 68hc11 (spi) interface ad420 to microwire interface the flexible serial interface of the ad420 is also compatible with the national semiconductor microwire interface. the microwire interface is used in microcontrollers such as the cop400 and cop800 series of processors. a generic interface to use the microwire interface is shown in figure 11. the g1, sk, and so pins of the microwire interface are respec- tively connected to the latch, clock, and data in pins of the ad420. data in clock latch so sk ad420 microwire g1 figure 11. ad420 to microwire interface external boost function the external boost transistor reduces the power dissipated in the ad420 by reducing the current flowing in the on-chip output transistor (dividing it by the current gain of the external circuit). a discrete npn transistor with a breakdown voltage, bv ceo , greater than 32 v can be used as shown in figure 12. boost i out rload ad420 19 18 mjd31c or 2n3053 1k w 0.022? figure 12. external boost configuration the external boost capability has been developed for those users who may wish to use the ad420, in the soic package, at the extremes of the supply voltage, load current, and temperature range. the pdip package (because of its lower thermal resis- tance) will operate safely over the entire specified voltage, tem- perature, and load current ranges without the boost transistor. the plot in figure 13 shows the safe operating region for both package types. the boost transistor can also be used to reduce the amount of temperature induced drift in the part. this will minimize the temperature induced drift of the on-chip voltage reference, which improves drift and linearity. v cc 28v 20v 12v 4v ?0 ?0 ?0 0 20 40 60 80 100 temperature ? c 25v when using soic packaged devices, an external boost transistor is required for operation in this area ad420 or ad420-32 32v figure 13. safe operating region
rev. c C10C ad420 ad420 protection transient voltage protection the ad420 contains esd protection diodes which prevent damage from normal handling. the industrial control environ- ment can, however, subject i/o circuits to much higher tran- sients. in order to protect the ad420 from excessively high voltage transients such as those specified in iec 801, external power diodes and a surge current limiting resistor may be re- quired, as shown in figure 14. the constraint on the resistor is that during normal operation the output voltage level at i out must remain within its voltage compliance limit ( i out ( rp + r load ) v cc C 2.5 v ) and the two protection diodes and resistor must have appropri- ate power ratings. i out gnd v cc r p r load v cc ad420 figure 14. output transient voltage protection board layout and grounding the ad420 ground pin, designated gnd, is the high quality ground reference point for the device. any external loads on the ref out and v out pins of the ad420 should be returned to this reference point. analog and digital ground currents should not share a common path. each signal should have an appropri- ate analog or digital signal return routed close to it. using this approach, signal loops enclose a small area, minimizing the in- ductive coupling of noise. wide pc tracks, large gauge wire, and ground planes are highly recommended to provide low imped- ance signal paths. power supplies and decoupling the ad420 supply pins, v cc (pin 23) and v ll (pin 2), should be decoupled to gnd with 0.1 m f capacitors to eliminate high frequency noise that may otherwise get coupled into the analog system. high frequency ceramic capacitors are recommended. the decoupling capacitors should be located in close proximity to the pins and the ground line to have maximum effect.
rev. c C11C ad420 outline dimensions dimensions shown in inches and (mm). n-24 24-lead plastic dip 24 112 13 1.275 (32.30) 1.125 (28.60) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) min 0.070 (1.77) 0.045 (1.15) 0.200 (5.05) 0.125 (3.18) 0.210 (5.33) max 0.100 (2.54) bsc 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) r-24 24-lead small outline (soic) 24 13 12 1 0.6141 (15.60) 0.5985 (15.20) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45
C12C printed in u.s.a. c1870cC2C11/95

▲Up To Search▲

Price & Availability of 420AR-32

	To Download 420AR-32 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .